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SV51006
2014.01.10
I/O Pins Features for Stratix V Devices
5-21
V OD swing reduces power consumption. You can statically adjust the V OD of the differential signal by
changing the V OD settings in the Quartus II software Assignment Editor.
Figure 5-4: Differential V OD
This figure shows the V OD of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
V OD
Negative Channel (n)
V CM
Ground
Differential Waveform
V OD (diff peak - peak) = 2 x V OD (single-ended)
V OD
p-n=0V
V OD
Table 5-14: Quartus II Software Assignment Editor — Programmable V OD
This table lists the assignment name for programmable V OD and its possible values in the Quartus II software
Assignment Editor.
To
Assignment name
Allowed values
Field
Assignment (Default setting in bold)
tx_out
Programmable Differential Output Voltage (V OD )
0 (low), 1 (medium low), 2 (medium high), 3 (high)
Related Information
Programmable IOE Features in Stratix V Devices on page 5-17
I/O Pins Features for Stratix V Devices
Open-Drain Output
The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured
as an open drain, the logic value of the output is either high-Z or logic low.
Use an external resistor to pull the signal to a logic high.
Bus-Hold Circuitry
Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device
enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the
configuration.
The bus-hold circuitry uses a resistor with a nominal resistance (R BH ), approximately 7 k Ω , to weakly pull
the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next
I/O Features in Stratix V Devices
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